1. Field of the Invention
The present invention relates to a circuit for distributing an ignition signal on every cylinder individually of a multicylinder engine principally for automobile.
2. Description of the Prior Art
FIG. 1 shows a configuration of a conventional ignition signal distributing circuit for a multicylinder engine.
FIG. 1, numeral 1 designates an RS flip-flop having a reset input terminal R of negative logic. An output signal S.sub.G of a cylinder identifying sensor 50 of an engine (not shown) is inputted to an input terminal S of this RS flip-flop 1, and an output signal S.sub.CR of a crank angle sensor 51 is inputted to a reset input terminal R thereof, respectively.
The cylinder identifying sensor 50 identifies that a first cylinder and a fourth cylinder of the engine are to be ignited, and at this time, outputs a cylinder identification signal by turning the output signal S.sub.G to the logic level "1".
Also, the crank angle sensor 51 outputs a crank angle signal by turning the output signal S.sub.CR to "1" when each cylinder of the engine is positioned in a predetermined crank angle section.
In FIG. 1, numeral 2 designates an ignition signal arithmetic unit, which inputs the output signal S.sub.G of the cylinder identifying sensor 50 and the output signal S.sub.CR of the crank angle sensor 51, and operates and outputs signals for ignition signal Sc and Sd on the basis of information on the both signals.
Numeral 3 designates a two-input NAND gate, which inputs the output signal S.sub.CR of the crank angle sensor 51 and an output signal Sa from an inversion output terminal Q of the RS flip-flop 1, and outputs a signal Sb.
Numerals 4 and 5 designate two-input NOR gates, and numerals 6 and 7 designate AND gates of one-inversion-input type, and to one input terminal of each gate, a cranking switch signal S.sub.SW is inputted. Also, an output signal Sc of the ignition signal arithmetic unit 2 is inputted to the other input terminal of the NOR gate 4, and an output signal Sd of the ignition signal arithmetic unit 2 is inputted to the other input terminal of the NOR gate 5, respectively. The output signal Sa of the RS flip-flop 1 is inputted to the inversion input terminal of the one-inversion-input type AND gate 6, and the output signal Sb of the NAND gate 3 is inputted to the inversion input terminal of the one-inversion-input type AND gate 7, respectively.
Numeral 8 designates a two-input OR gate, whereto each output signal of the NOR gate 4 and the AND gate 6 is inputted. This OR gate 8 distributes a first ignition signal S.sub.IG1 to the first cylinder #1 and the fourth cylinder #4 of the engine.
Also, numeral 9 designates a two-input OR gate, whereto each input signal of the NOR gate 5 and the AND gate 7 is inputted. This OR gate 9 distributes a second ignition signal S.sub.IG2 to the second cylinder #2 and the third cylinder #3 of the engine.
FIG. 2 is a table showing the state of the inversion output terminal Q responding to the both inputs of the RS flip-flop 1, that is, the state of the output signal Sa. Note that a mark "*" in the Q column shows that the state is the same as the previous state.
FIG. 3 is a waveform diagram showing a signal waveform at each position of the conventional ignition signal distributing circuit for engine shown in FIG. 1.
When power is turned on at a time t1, a cranking switch (not shown) for supplying power to a starter (not shown) is operated from OFF to ON at a time t2, and the cranking switch signal S.sub.SW is turned to "1". When the output signal S.sub.CR of the crank angle sensor 51 is kept intact at the level "0" at this time, thereafter the first and the second ignition signals S.sub.IG1 and S.sub.IG2 are outputted alternately at a predetermined timing from the OR gates 8 and 9.
Hereinafter, detailed description is made thereon.
In the case where the output signal S.sub.G of the cylinder identifying sensor 50 and the output signal S.sub.CR of the crank angle sensor 51 are both "0", the Q output signal Sa of the RS flip-flop 1 whereto the both signals are inputted is turned to "1". Thereafter, the signal Sa is not changed even when the output signal S.sub.CR of the crank angle sensor 51 is turned to "1".
In th case where the cranking switch signal S.sub.SW is "1", the NOR gates 4 and 5 are disabled, and the one-inversion-input type AND gates 6 and 7 are enabled. Also, the output signal Sb of the NAND gate 3 is turned to "0" only when both of the Q output signal Sa of the RS flip-flop 1 and the output signal S.sub.CR of the crank angle sensor 51 are "1". Accordingly, the output signal of the one-inversion-input type AND gate 7 turning the signal Sb from "0" to "1" is turned to "1", and the second ignition signal S.sub.IG2 is outputted from the OR gate 9.
Also, in the case where the cranking switch signal S.sub.SW is "0", the NOR gates 4 and 5 are enabled, and the one-inversion-input type AND gates 6 and 7 are disabled. Accordingly, when the signal Sd is "0", the output of the NOR gate 5 is turned to "1", and the second ignition signal S.sub.IG2 is outputted from the OR gate 9.
The signal Sd has nearly the same phase and the same waveform as those of the signal Sb.
Also, the Q output signal Sa of the RS flip-flop 1 is turned to "1" when both of the signals S.sub.G and S.sub.CR to the RS flip-flop 1 are "0", and thereafter it is turned to "0" when the output signal S.sub.G of the cylinder identifying sensor 50 and the output signal S.sub.CR of the crank angle sensor 51 are both turned to "1", and is turned again to "1" when the output signal S.sub.CR of the crank angle sensor 51 is turned to "0".
In the case where the cranking switch signal S.sub.SW is " 1", when the output signal Sa of the RS flip-flop 1 is "0", the output of the one-inversion-input type AND gate 6 is turned to "1", and the first ignition signal S.sub.IG1 is outputted from the OR gate 8.
Also, in the case where the cranking switch signal S.sub.SW is "0", if the signal Sc is "0", the output signal of the NOR gate 4 is turned to "1", and the first ignition signal S.sub.IG1 is outputted from the OR gate 8.
The signal Sc has nearly the same phase and the same waveform as those of the signal Sa.
The conventional ignition signal distributing circuit for engine is constituted as described above, and therefore, for example, as shown in FIG. 4, power is turned on at a timer t3, and thereafter the cranking switch signal S.sub.SW is turned to ON ("1") at a time t5 before a time t6, and the output signal S.sub.CR of the crank angle sensor 51 is turned to "1" between the time t3 and the time t6. Between the time t3 and the time t6, "0" is inputted to the set input terminals of the RS flip-flop 1, and "1" is inputted to the inversion reset input terminal R thereof. In this case, the Q output signal Sa of the RS flip-flop 1 becomes *, and can take either value, "0" or "1". Assuming that it is turned to "0", since the output signal of the one-inversion-input type AND gate 6 depends on the cranking switch signal S.sub.SW, it is turned to "1" between the time t5 and the time t6. Consequently, the first ignition signal S.sub.IG1 of "1" is outputted from the OR gate 8, and thereafter at the time t6, the both input signals S.sub.G and S.sub.CR of the RS flip-flop 1 are turned to "0", and therefore the Q output signal Sa is turned to "1", and the output of the one-inversion-input type AND gate 6 is turned to "0", and therefore the output of the OR gate 8 is turned to "0". For this reason, a problem is raised that the first ignition signal S.sub.IG1 is generated during a duration of time between t5 and t6 when normally operating, the first ignition signal S.sub.IG1 must not be generated.